数字缓冲 - 工作，定义，真相表，双重反转，扇出

缓冲阶段基本上是增强中间级，允许输入电流到达输出而不会受到输出负载的影响。

在这篇文章中，我们将尝试了解数字缓冲区是什么，我们将通过逻辑“不是”门，数字缓冲器扇出风扇，三态缓冲区，查看其定义，符号，真相，双重反演，查看了它的定义，符号，真相，双重反转，TRI状态缓冲交易所交换机等效，有源“高”三态缓冲区，有源“高”反相三态缓冲器，有源“低”状态三态缓冲器，有源“低”反相三态缓冲器，三态缓冲器控制，三态缓冲区数据总线控件，最后我们将概述常见的数字缓冲区和三态缓冲区IC。

In one of the previous posts we learned about logic “NOT” gate which is also called digital inverter. In a NOT gate output is always complementary to input.

因此，如果输入是“高”输出转动“低”，如果输入是“低”输出变频器，则称为逆变器。

可能存在需要从输入中分离或隔离的输出，或者在输入可能相当弱的情况下并且需要驱动需要更高电流的负载，而不使用中继或晶体管等反转信号的极性。在这种情况下，数字缓冲器变得有用，并且有效地应用于信号源和实际负载驱动器级之间的缓冲器。

Suchlogic gateswhich can deliver signal output same as input and act as intermediate buffer stage is called digital buffer.

A digital buffer does not perform any inversion of the fed signal and it is not a "decision making" device either, like logic “NOT” gate, but gives out the same output as input.

Illustration of Digital Buffer:

The above symbol is similar to logic “NOT” gate without the “o” at the tip of the triangle, which means that it does not perform any inversion.

The Boolean equation for the digital buffer is Y = A.

“Y”是输入和“A”输出。

Truth table:

双重反转使用逻辑“不是”门：

可以使用以下方式使用两个逻辑“不是”栅栏来构造数字缓冲器：

输入信号首先通过左手侧的第一不是栅极反转，然后通过右手侧的下一个“不是”栅极进一步反转反转信号，这使得输出与输入相同。

Why Digital Buffers are Used

现在你可能会挠你的头数码网络的原因tal buffer even exist, it does not do any operation like other logic gates, we could just throw the digital buffer out of a circuit and connect a piece of wire…….correct? Well not really.

Here is the answer: A logic gate does not require a high current to perform any operations. It just requires a voltage level (5V or 0V) at low current is enough.

All types of logic gates primarily support a built in amplifier so that the output is not dependent on input signals. If we cascade two logic “NOT” gates in series we get same signal polarity as input at the output pin but, with relatively higher current. In other words digital buffer works like a digital amplifier.

A digital buffer can be used as an isolation stage between signal generator stages and driver stages; also it helps prevent impedance affecting one circuit from another.

A digital buffer can provide higher current capability which can be used for driving switching transistors more efficiently.

The digital buffer provides higher amplification which is also called “fan-out” capability.

数字缓冲扇出功能：

扇出: The fan-out can be defined as the number of logic gates or digital ICs that can be driven in parallel by a digital buffer (or any digital ICs).

A typical digital buffer has fan-out of 10, which means the digital buffer can drive 10 digital ICs in parallel.

粉丝：粉丝是数字逻辑门或数字IC可接受的数字输入的数量。

In the above schematic the digital buffer has fan-in of 1, which means one input. A ‘2-input’ logic “AND” gate has fan-in of two and so on.

From the above schematic a buffer is connected to the 3 inputs of three different logic gates.

If we just connect a piece of wire in the place of the buffer in the above circuit, the input signal might not be with sufficient current and causes voltage to drop across gates and might not even recognize the signal.

So in conclusion a digital buffer is used for amplifying a digital signal with higher current output.

Tri-state Buffer

Now we know what a digital buffer does and why it exists in electronic circuits. These buffers have two states “HIGH” and “LOW”. There is another type of buffer called “Tri-state buffer”.

This buffer has an additional pin called “Enable pin”. Using the enable pin we can connect or disconnect the output from input electronically.

Like a normal buffer, it works as digital amplifier and gives output signal same as the input signal, the only difference is that the output can be electronically connected and disconnected by the enable pin.

So a third state is introduced, in this the output is neither “HIGH” nor “LOW” but an open circuit state or high impedance at the output and will not respond to the input signals. This state is referred as “HIGH-Z” or “HI-Z”.

The above is the equivalent circuit of the tri-state buffer. The enable pin can connect or disconnect the output from the input.

There are four types of Tri-state buffer:
• Active “HIGH” Tri-state buffer
• Active “LOW” Tri-state buffer
• Active “HIGH” Inverting Tri-state buffer
• Active “LOW” Inverting Tri-state buffer
Let’s look each of them sequentially.

Active “HIGH” tri-state buffer

在主动“高”三态缓冲器（例如：74LS241）中，当我们在使能引脚处应用“高”或“1”或“高信号”时，输出引脚连接到输入引脚。

如果我们将“低”或“0”或负信号应用于使能引脚，则输出从输入断开连接，然后进入“HI-Z”状态，输出不会响应输入和输出将处于开路状态。

活动“低”三态缓冲区

Here the output will be connected to input when we apply “LOW” or “0” or negative signal at the enable pin.
If we apply “HIGH” or “1” or positive signal to enable pin, the output gets disconnected from input and output will be in “HI-Z” state / open circuit state.

Truth Table:

Active “HIGH” Inverting Tri-state Buffer

In active “HIGH” inverting Tri-state buffer (example: 74LS240), the gate act as logic “NOT” gate but, with the enable pin.

If we apply “HIGH” or “1” or positive signal at the enable input the gate gets activated and act like a regular logic “NOT” gate where its output is inversion / complementary of input.
If we apply “LOW” or “0” or negative signal to the enable pin, the output will be in “HI-Z” or open circuit state.

Truth table:

Active “LOW” Inverting Tri-state buffer:

在活跃的“低”反相三态缓冲, the gate acts as logic “NOT” gate but, with enable pin.

If we apply “LOW” or “0” or negative signal to enable pin, the gate activates and work like regular logic “NOT” gate.
如果我们应用“高”或“1”或正信号启用引脚，则输出引脚将处于“Hi-Z”状态/开路状态。

Truth Table:

三态缓冲器控制：

从上面我们看到缓冲器可以提供数字放大，三态缓冲器可以完全断开其从输入的输出并提供开路状态。

In this section we will learn about the application of the tri-state buffer and how it is used in digital circuits for managing data communication efficiently.

In digital circuits we can find a data bus / wires carrying data, they carry all kinds of data in a single bus to reduce wiring congestion / reduce PCB traces and also reducing manufacturing cost.

在总线的每一端，连接多个逻辑器件，微处理器和微控制器，该微控制器试图同时互相通信，该彼此进行传播，该彼此会产生一种被称为争用的东西。

Contention occurs in a circuit when some devices in a bus drives “HIGH” and some devices drives “LOW” simultaneously which causes short circuit and causes damage in a circuit.

Tri-state buffer can avoid such contention and properly send and receive data over a bus.

The tri-state buffer is used to isolate logic devices, microprocessors and microcontrollers from one another in a data bus. A decoder will allows only one set of tri-state buffers to pass data through the bus.

Say if the data set “A” is connected to a microcontroller, data set “B” to a microprocessor and data set “C” to some logic circuits.

In the above schematic all the buffers are active high tri-state buffer.

当解码器设置ENA“高”数据集“A”时，现在微控制器可以通过总线发送数据。

两个数据集“B”和“C”的其余部分处于“Hi-z”或非常高的阻抗状态，其将微处理器和逻辑电路从总线电隔离，该微控制器目前使用。

当解码器设置eNB“高”时，数据集“B”可以在总线上发送数据，并且数据集的其余部分“a”和“c”在“hi-z”状态下与总线隔离。同样，在启用数据集“C”时。

数据总线被任何数据集“A”或“B”或“C”在给定时间以防止争用。

我们还可以通过在并联和相反方向上连接两个三态缓冲区来建立双面（双向）通信。使能引脚可用作方向控制。对于这种类型的应用，可以使用IC 74245。

Here are the commonly available list of digital buffers and Tri-state buffers:

•74LS07十六进制非反相缓冲区
• 74LS17 Hex Buffer/Driver
• 74LS244 Octal Buffer/Line Driver
• 74LS245 Octal Bi-directional Buffer
• CD4050 Hex Non-inverting Buffer
• CD4503 Hex Tri-state Buffer
• HEF40244 Tri-state Octal Buffer

这结论是我们对数字缓冲工作的讨论以及它们的各种数字配置，我希望它能够很好地了解细节。如果您有任何其他问题或建议，请在评论部分中表达您的问题，您可以快速回复。